The present invention relates to a gate array semiconductor integrated circuit (IC) device.
A gate array IC device, in which bonding pads and input/output buffer regions are arranged in peripheral portions of a semiconductor chip and a macrocell region and an internal gate region are arranged in central portions of the semiconductor chip, is called as a composite type gate array semiconductor IC device.
A gate array device is realized in general by preparing a suitably impurity-diffused master wafer and customizing various functions thereof by a wiring step. In such a wiring step, a computer aided design (CAD) technique is used to design a desired wiring pattern.
In the macrocell region, a plurality of macro cells such as memory cells are formed, and set internal wirings previously designed and registered are formed so as to realize a previously determined memory and/or logic function. When the function of the macro cells is to be realized by using internal gates, an area therefor is increased with performance degraded. Therefore, such a macrocell region is designed at high density and disposed in a specific region of the chip by the registered wiring pattern.
In the internal gate region, a plurality of internal gates are formed, and function blocks (FBs) such as flip-flop are realized by combining the internal gates using a specific or personal wiring pattern by an automatic wiring design technique of CAD to satisfy the requirement of the customer.
In the input/output buffer regions, a plurality of input/output buffers are arranged, and the input/output buffers have functions such as level shift and external load which are different from the functions in the internal gate region. Therefore, the input/output buffer regions are excluded from the scope of the automatic wiring by CVD.
On a conventional composite type gate array semiconductor IC device, wiring channel regions are provided between the macrocell region and the input/output buffer regions and/or between one macrocell region and another macrocell region so as to only form thereon wirings for connecting the internal gate region and the input/output buffer region. Under the wiring channel regions, any circuit element constituting the macrocell or the input/output buffer is not formed and any internal wiring belonging within the macrocell region or the input/output buffer region is not formed. When the area of the wiring channel region is too small, the automatic wiring design by CAD technique becomes impossible. Alternately, when such a region is too large, the effective area ratio to the total area of the semiconductor chip of the device is decreased, and therefore, for example, the number of internal gates may be reduced.